Memory Cells, Memory Cell Programming Methods, Memory Cell Reading Methods, Memory Cell Operating Methods, and Memory Devices

ABSTRACT

Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In one embodiment, a memory cell includes a wordline, a first bitline, a second bitline, and a memory element. The memory element is electrically connected to the wordline and selectively electrically connected to the first bitline and the second bitline. The memory element stores information via a resistive state of the memory element. The memory cell is configured to convey the resistive state of the memory element via either a first current flowing from the first bitline through the memory element to the wordline or a second current flowing from the wordline through the memory element to the second bitline.

TECHNICAL FIELD

Embodiments disclosed herein pertain to memory cells, memory cellprogramming methods, memory cell reading methods, memory cell operatingmethods, and memory devices.

BACKGROUND

Resistive random access memories may use a material capable of beingconfigured in one of two different resistive states to storeinformation. When configured in one of the resistive states, thematerial may have a high resistance to electrical current. In contrast,when configured in the other resistive state, the material may have alow resistance to electrical current. The resistive state in which thematerial is configured may be changed using electrical signals. Forexample, if the material is in a high-resistance state, the material maybe configured to be in a low-resistance state by applying a voltageacross the material.

The resistive state may be persistent. For example, once configured in aresistive state, the material may stay in the resistive state even ifneither a current nor a voltage is applied to the material. Furthermore,the configuration of the material may be repeatedly changed from thehigh resistance state to the low resistance state or from the lowresistance state to the high resistance state.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a chart illustrating voltage/current relationships.

FIG. 2 is chart illustrating other voltage/current relationships.

FIG. 3 is a schematic diagram of a memory cell.

FIG. 4 is a schematic diagram of a memory device.

FIG. 5 is a schematic diagram of a memory device illustrating a current.

FIG. 6 is a schematic diagram of a memory device illustrating anothercurrent.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Embodiments of the invention encompass memory cell operating methods,memory cell programming methods, memory cell reading methods, memorycells, and memory devices. Example embodiments of such methods, memorycells, and memory devices are described with reference to FIGS. 1-6.

Random access memories may use resistive states of a memory element tostore one or more bits of information. For example, a memory elementcapable of being configured in either a high-resistance state or alow-resistance state may store one bit of information by associating abit value of “1” with the low-resistance state and a bit value of “0”with the high-resistance state. Alternatively, a bit value of “1” may beassociated with the high-resistance state and a bit value of “0” may beassociated with the low-resistance state.

The memory element may include a bipolar memory material. A positivevoltage applied across the bipolar memory material may change theconfiguration of the bipolar memory material from a high-resistancestate to a low-resistance state. Furthermore, a negative voltage appliedacross the bipolar memory material may change the configuration of thebipolar memory material from a low-resistance state to a high-resistancestate.

Alternatively, a negative voltage applied across the bipolar memorymaterial may change the configuration of the bipolar memory materialfrom a high-resistance state to a low-resistance state and a positivevoltage applied across the bipolar memory material may change theconfiguration of the bipolar memory material from a low-resistance stateto a high-resistance. Accordingly, a bipolar memory material may beconfigured in a first resistive state using a voltage having a firstpolarity and may be configured in a second resistive state using avoltage having a polarity opposite that of the first polarity.

Examples of bipolar memory material include ionic conductingchalcogenides, binary metal oxides, perovskite oxides, colossalmagnetoresistives, and polymers. Example ionic conducting chalcogenidesthat may be used as bipolar memory material include GeS, GeSe and Ag orCu-doped GeS and GeSe. Example binary metal oxides that may be used asbipolar memory material include HfO_(x), Nb₂O₅, Al₂O₃, WO_(x), Ta₂O₅,TiO_(x), ZrO_(x), Cu_(x)O, and Ni_(x) O. Example ionic perovskite oxidesthat may be used as bipolar memory material include doped or undopedSrTiO₃, SrZrO₃, BaTiO₃.

Example colossal magnetoresistives that may be used as bipolar memorymaterial include Pr_(1-x)Ca_(x)MnO₃ (PCMO), La_(1-x)Ca_(x)MnO₃ (LCMO),and Ba_(1-x) Sr_(x)TiO₃. Example polymers that may be used as bipolarmemory material include Bengala Rose, AlQ₃Ag, Cu-TCNQ, DDQ, TAPA, andfluorescine-based polymers. Of course, other materials may be used asbipolar memory material. The materials listed above are provided by wayof example rather than as an exhaustive list of bipolar memory material.

Referring to FIG. 1, a chart 100 depicts one example of a relationship102 between voltages applied to a memory element initially in ahigh-resistance state and currents through the memory element resultingfrom the voltages. The memory element may comprise one or more of thebipolar memory materials described above. Chart 100 illustrates that asvoltages applied to the memory element increase from −0.6 V to 0.2 V, nocurrent, or a negligible amount of current, for example less than 1micro amp, flows through the memory element. However, at a voltagesubstantially equal to a turn-on voltage 104, the memory element beginsconducting current. As the voltage across the memory element isincreased beyond turn-on voltage 104, the amount of current conducted bythe memory element increases with the voltage without current clamping.The flattening of the current with voltage depicted in FIG. 1 resultsfrom current clamping of a measurement circuit.

Thus, chart 100 illustrates a change in the resistive state of thememory element. Initially, the memory element is in a high-resistancestate as evidenced by the fact that the memory element does not conductcurrent or conducts a negligible amount of current when voltages smallerthan the turn-on voltage are applied to the memory element. In thishigh-resistance state, the memory element may have a resistance of aboutor above 10⁹ ohms. However, once a voltage greater than or equal toturn-on voltage 104 is applied to the memory element, the memory elementconfigures itself in a low-resistance state as evidenced by the factthat the memory element begins conducting current. In thislow-resistance state, the memory element may be highly conductive andhave a resistance of about a few thousand ohms.

Referring to FIG. 2, a chart 200 depicts one example of a relationship202 between voltages applied to a memory element initially in thelow-resistance state described above and currents running through thememory element resulting from the voltages. Chart 200 illustrates thatcurrents resulting from voltages greater than about 0.25 V aresubstantially the same, which results from current clamping of ameasurement circuit. Without the current clamping, the current increaseswith voltage. As the voltage is decreased below about 0.25 V, thecurrent through the memory element accordingly decreases. As the voltageapplied across the memory element becomes negative, the current throughthe memory element is also negative. However, when the voltage appliedacross the memory element is substantially equal to a turn-off voltage204, the amount of current through the memory element is substantiallyzero. As the voltage is further decreased below the turn-off voltage,the current through the memory element remains substantially zero.

Thus, chart 200 illustrates a change in resistive state of the memoryelement. Initially, the memory element is in the low-resistance state asevidenced by the fact that the memory element conducts current whenvoltages greater than turn-off voltage 204 are applied to the memoryelement. However, once a voltage less than or equal to turn-off voltage204 is applied to the memory element, the memory element configuresitself in the high-resistance state described above as evidenced by thefact that the memory element stops conducting current or conducts only anegligible amount of current.

In some cases, once configured in the high-resistance state, the memoryelement may remain in the high-resistance state as long as a voltagegreater than or equal to turn-on voltage 104 is not applied to thememory element. The memory element may remain in the high-resistancestate even if no voltage is applied to the memory element. Accordingly,the high-resistance state of the memory element may be described asnon-volatile since the high-resistance state might not change over timeas long as a voltage greater than or equal to turn-on voltage 104 is notapplied to the memory element.

Similarly, in some cases, once configured in the low-resistance state,the memory element may remain in the low-resistance state as long as avoltage less than or equal to turn-off voltage 204 is not applied to thememory element. In fact, the memory element may remain in thelow-resistance state even if no voltage is applied to the memoryelement. Accordingly, the low-resistance state of the memory element mayalso be described as non-volatile since the low-resistance state mightnot change over time as long as a voltage less than or equal to turn-offvoltage 204 is not applied to the memory element.

Since the high-resistance state and the low-resistance state may benon-volatile, the memory element may be used to store one bitinformation. For example, a memory element may represent a bit value of“0” when configured in the high-resistance state and may represent a bitvalue of “1” when configured in the low-resistance state. Furthermore,the resistive state of the memory element may be repeatedly changed overtime. Accordingly, the memory element may be in the high-resistancestate representing a bit value of “0” at one moment in time and thememory element may be in a low-resistance state representing a bit valueof “1” at another moment in time. Similarly, the representation of bitvalue with resistance states can be the opposite of that describedabove.

Referring to FIG. 3, a memory cell 300 is illustrated. Memory cell 300includes a memory element 302 having electrodes 306 and 304. Memoryelement 302 may comprise a bipolar memory material such as one or moreof the bipolar memory materials discussed above. Memory cell 300 alsoincludes a wordline 308 and two bitlines 314 and 316. Electrode 304 ofmemory element 302 is connected to a wordline 308.

Bitline 314 may be selectively electrically connected to memory element302. For example, a diode 310 may be connected to bitline 314 and toelectrode 306. When diode 310 is forward biased (e.g., forward biasedbeyond a cut-in voltage of diode 310), diode 310 may conduct currentfrom bitline 314 to memory element 302, thereby electrically connectingbitline 314 to memory element 302. In contrast, when diode 310 is notforward biased (e.g., when diode 310 is reverse biased), diode 310 mayhinder current from flowing from memory element 302 to bitline 314 orfrom bitline 314 to memory element 302 so that memory element 302 is notelectrically connected to bitline 314.

Similarly, bitline 316 may be selectively electrically connected tomemory element 302. For example, a diode 312 may be connected to bitline316 and to electrode 306. When diode 312 is forward biased (e.g.,forward biased beyond a cut-in voltage of diode 312), diode 312 mayconduct current from memory element 302 to bitline 316 therebyelectrically connecting memory element 302 to bitline 316. In contrast,when diode 312 is not forward biased (e.g., when diode 312 is reversebiased), diode 312 may hinder current from flowing from bitline 316 tomemory element 302 or from memory element 302 to bitline 316 so thatmemory element 302 is not electrically connected to bitline 316.

In some configurations, a memory cell may comprise one or more devicesthat selectively electrically connect a memory element to a firstbitline and/or a second bitline instead of diodes. For example, in oneconfiguration, memory element 300 may use a first transistor in place ofdiode 310 and a second transistor in place of diode 312. When turned on,the first transistor may allow current to flow between bitline 314 andmemory element 302, electrically connecting bitline 314 and memoryelement 302. When turned off, the first transistor may hinder currentfrom flowing between bitline 314 and memory element 302 therebyelectrically disconnecting bitline 314 and memory element 302.

Similarly, the second transistor may selectively electrically connectmemory element 302 to bitline 316. Devices other than diodes ortransistors may alternatively be used to selectively electricallyconnect memory element 302 to bitlines 314 and 316.

Memory cell 300 may store a bit of information via a resistive state ofmemory element 302. In one configuration, the bit may have a value of“0” or a value of “1.” For example, according to one convention, ifmemory element 302 is in a high-resistance state, the value of the bitstored by memory cell 300 may be “0” and if memory element 302 is in alow-resistance state, the value of the bit stored by memory cell 300 maybe “1.” Of course, a convention in which a high-resistance staterepresents a bit value of “1” and a low-resistance state represents abit value of “0” may alternatively be used.

A read operation may be used to determine a value of a bit stored bymemory cell 300. According to one read operation, a first positivevoltage may be applied between wordline 308 and bitline 316 so thatwordline 308 is at a higher potential than bitline 316 and so that diode312 is forward biased. The first positive voltage may be greater than acut-in voltage of diode 312 but less than a sum of the cut-in voltage ofdiode 312 and the turn-off voltage (which was described above inrelation to FIG. 2) of memory element 302 so that the resistive state ofmemory element 302 is not altered. A second positive voltage may besimultaneously applied between wordline 308 and bitline 314 so thatwordline 308 is at a higher potential than bitline 314 and so that diode310 is reverse biased. The second voltage may be lower than a breakdownvoltage of diode 310. In some cases, the first voltage and the secondvoltage may be substantially the same voltage.

If memory element 302 is configured in a low-resistance state, currentmay flow from wordline 308 through memory element 302 and forward-biaseddiode 312 to bitline 316. Based on the current, a memory devicecomprising memory cell 300 may determine that memory element 302 is in alow-resistance state and therefore the value stored by memory cell 300is a “1.” For example, the memory device may compare the current onbitline 316 with a reference current or the memory device may use thecurrent on bitline 316 to create a voltage and may then compare thevoltage with a reference voltage.

In contrast, if memory element 302 is configured in a high-resistancestate, memory element 302 may hinder current from flowing from wordline308 through memory element 302 and forward-biased diode 312 to bitline316. Alternatively, memory element 302 may restrict an amount of currentflowing from wordline 308 through memory element 302 and forward-biaseddiode 312 to bitline 316 to a negligible amount of current that may beclearly distinguished from an amount of current allowed to flow whenmemory element 302 is in the low-resistance state. Based on the lack ofcurrent, or the very small amount of current, the memory devicecomprising memory cell 300 may determine that memory element 302 is inthe high-resistance state and therefore the value stored by memory cell300 is a “0.”

Another method of reading memory cell 300 may alternatively be used.According to this method, a first positive voltage may be appliedbetween bitline 314 and wordline 308 so that bitline 314 is at a higherpotential than wordline 308 and so that diode 310 is forward biased. Thefirst positive voltage may be greater than the cut-in voltage of diode310 but less than a sum of the cut-in voltage of diode 310 and theturn-on voltage (which was described above in relation to FIG. 1) ofmemory element 302 so that the resistive state of memory element 302 isnot altered. A second positive voltage may simultaneously be appliedbetween bitline 316 and wordline 308 so that bitline 316 is at a higherpotential than wordline 308 and so that diode 312 is reverse biased. Thesecond voltage may be lower than a breakdown voltage of diode 312. Insome cases, the first voltage and the second voltage may besubstantially the same voltage.

If memory element 302 is configured in a low-resistance state, currentmay flow from bitline 314 through forward-biased diode 310 and memoryelement 302 to wordline 308. Based on the current on wordline 308, amemory device comprising memory cell 300 may determine that memoryelement 302 is in a low-resistance state and therefore the value storedby memory cell 300 is a “1.”

In contrast, if memory element 302 is configured in a high-resistancestate, memory element 302 may hinder current from flowing from bitline314 through forward-biased diode 310 and memory element 302 to wordline308. Alternatively, memory element 302 may restrict an amount of currentflowing from bitline 314 through forward-biased diode 310 and memoryelement 302 to wordline 308 to a negligible amount that may be clearlydistinguished from an amount of current allowed to flow when memoryelement 302 is in the low-resistance state. Based on the lack ofcurrent, or the very small amount of current, the memory devicecomprising memory cell 300 may determine that memory element 302 is inthe high-resistance state and therefore the value stored by memory cell300 is a “0”.

In addition to reading a bit value from memory cell 300, a bit value maybe written to memory cell 300. To write a bit value of “1” to memorycell 300, a first positive voltage may be applied between bitline 314and wordline 308 so that bitline 314 is at a higher potential thanwordline 308 and so that diode 310 is forward biased. The first positivevoltage may be greater than a sum of the cut-in voltage of diode 310 andthe turn-on voltage of memory element 302. If memory element 302 is in ahigh-resistance state, the first voltage (or a current resulting fromthe first voltage) may re-configure memory element 302 to be in alow-resistance state. If memory element 302 is already in alow-resistance state, memory element 302 may remain in thelow-resistance state. Consequently, due to the first voltage, memoryelement 302 may be configured in a low-resistance state correspondingwith a bit value of “1.”

A second positive voltage may be applied simultaneously with the firstvoltage. The second positive voltage may be applied between bitline 316and wordline 308 so that bitline 316 is at a higher potential thanwordline 308 and so that diode 312 is reverse biased. The second voltagemay hinder current from flowing from bitline 314 to bitline 316. Thesecond voltage may be lower than a breakdown voltage of diode 312.

The first voltage may result from a first voltage pulse and the secondvoltage may result from a second voltage pulse. In some cases, the firstvoltage and the second voltage may be substantially the same voltage.

Alternatively, a bit value of “0” may be written to memory cell 300. Towrite a bit value of “0” to memory cell 300, a first positive voltagemay be applied between wordline 308 and bitline 316 so that wordline 308is at a higher potential than bitline 316 and so that diode 312 isforward biased. The first positive voltage may be greater than a sum ofthe cut-in voltage of diode 312 and the turn-off voltage of memoryelement 302. If memory element 302 is in a low-resistance state, thefirst voltage (or a current resulting from the first voltage) mayre-configure memory element 302 to be in a high-resistance state. Ifmemory element 302 is already in a high-resistance state, memory element302 may remain in the high-resistance state. Consequently, due to thefirst voltage, memory element 302 may be configured in a high-resistancestate corresponding with a bit value of “0.”

A second positive voltage may be applied simultaneously with the firstvoltage. The second positive voltage may be applied between wordline 308and bitline 314 so that wordline 308 is at a higher potential thanbitline 314 and so that diode 310 is reverse biased. The second voltagemay hinder current from flowing from bitline 316 to bitline 314. Thesecond voltage may be lower than a breakdown voltage of diode 310.

The first voltage may result from a first voltage pulse and the secondvoltage may result from a second voltage pulse. In some cases, the firstvoltage and the second voltage may be substantially the same voltage.

The methods of writing a “0” and writing a “1” to memory cell 300 may berepeatedly used so that memory cell 300 stores different bit values overtime. In some cases, memory element 302 may be re-written using thesemethods millions of times without damaging memory element 302. Sincememory element 302 may remain in a resistive state without a voltage orcurrent being applied to memory element 302 as was discussed above inrelation to FIG. 1, memory element 302 may be said to preserve a bitvalue in a non-volatile manner. Accordingly, memory cell 300 may store abit of information without having to be frequently refreshed or memorycell 300 may be refreshed at a rate lower than a rate used to refresh avolatile memory cell.

Referring to FIG. 4, a schematic diagram 400 of a portion of a memorydevice is illustrated. The memory device includes memory cell 300 aswell as additional memory cells 402, 404, 406, 408, 410, 412, 414, and416. The memory device may store a plurality of bits. For example, thememory device may store one bit in each memory cell of the memorydevice.

The memory cells of the memory device may be arranged to share bitlinesand wordlines. In diagram 400, memory cells 402, 408, and 412 sharewordline 418; memory cells 404, 300, and 414 share wordline 308; andmemory cells 406, 410, and 416 share wordline 420. Furthermore, indiagram 400, memory cells 402, 404, and 406 share bitlines 424 and 426;memory cells 408, 300, and 410 share bitlines 314 and 316; and memorycells 412, 414, and 416 share bitlines 428 and 430.

Referring to FIG. 5, a schematic diagram 500 illustrating aconfiguration of the memory device of FIG. 4 is illustrated. Theconfiguration may be used to write a bit value of “1” to memory cell 300or to read a bit of information from memory cell 300. According to theconfiguration, a first positive voltage is applied across bitline 314and wordline 308. A second positive voltage is applied across bitline316 and wordline 308. Consequently, a current may flow from bitline 314through memory cell 300 to wordline 308 as illustrated by arrow 502 andas was described above in relation to FIG. 3. If the first voltage isgreater than a sum of the cut-in voltage of diode 310 and the turn-onvoltage of memory element 302, a “1” may be written to memory cell 300as was described above in relation to FIG. 3.

Alternatively, if the first voltage is greater than the cut-in voltageof diode 310 but less than a sum of the cut-in voltage of the diode andthe turn-on voltage of memory element 302, the memory device maydetermine the value of a bit stored by memory cell 300 based on acurrent flowing from bitline 314 to wordline 308 as was described abovein relation to FIG. 3.

It may be desirable to ensure that values stored by memory cells 402,404, 406, 408, 410, 412, 414, and 416 are not disturbed while writing orreading memory cell 300. To avoid disturbances, bitlines and wordlinesof the memory device may be configured with particular voltages.

For example, when writing a “1” into memory cell 300, bitlines 314 and316 may be at a higher potential than wordline 308. Since memory cells408 and 410 are also connected to bitlines 314 and 316, wordlines 418and 420 may be configured to be at substantially the same potential asbitlines 314 and 316 to hinder current from flowing from bitline 314and/or bitline 316 to wordline 418 and/or wordline 420.

Furthermore, it may be desirable to hinder currents from flowing frommemory cells 404 and 414 onto wordline 308 so that a current on wordline308 may be correctly attributed to memory cell 300. To do so, bitlines424 and 428 may be configured to be at substantially the same potentialas wordline 308 to hinder current from flowing from bitline 424 towordline 308 via memory cell 404 and to hinder current from flowing frombitline 428 to wordline 308 via memory cell 414. In addition, bitlines426 and 430 may be configured at a higher potential than wordline 308 sothat current is hindered from flowing from bitline 426 through memorycell 404 to wordline 308 and from bitline 430 through memory cell 414 towordline 308.

Other memory cells not connected to either wordline 308 or bitlines 314and 316 (i.e., memory cells 402, 406, 412, and 416) may be configured tohinder consumption of current. For example, bitlines 424 and 426 andwordlines 418 and 420 may be configured with voltages causing the diodesof memory cells 402 and 406 to be reverse biased. Similarly, bitlines428 and 430 and wordlines 418 and 420 may be configured with voltagescausing the diodes of memory cells 412 and 416 to be reverse biased.

Referring to FIG. 6, a schematic diagram 600 illustrating aconfiguration of the memory device of FIG. 4 is illustrated. Theconfiguration may be used to write a bit value of “0” to memory cell 300or to read a bit of information from memory cell 300. According to theconfiguration, a first positive voltage is applied across wordline 308and bitline 316. A second positive voltage is applied across wordline308 and bitline 314. Consequently, a current may flow from wordline 308through memory cell 300 to bitline 316 as indicated by arrow 602 and aswas described above in relation to FIG. 3. If the first voltage isgreater than a sum of the cut-in voltage of diode 312 and the turn-offvoltage of memory element 302, a “0” may be written to memory cell 300as was described above in relation to FIG. 3.

Alternatively, if the first voltage is greater than the cut-in voltageof diode 312 but less than a sum of the cut-in voltage of diode and theturn-off voltage of memory element 302, the memory device may determinethe value of a bit stored by memory cell 300 based on a current flowingfrom wordline 308 to bitline 316 as was described above in relation toFIG. 3.

It may be desirable to ensure that values stored by memory cells 402,404, 406, 408, 410, 412, 414, and 416 are not disturbed while writing orreading memory cell 300. To avoid disturbances, bitlines and wordlinesof the memory device may be configured with particular voltages.

For example, when writing a “0” into memory cell 300, bitlines 314 and316 may be at a lower potential than wordline 308. Since memory cells408 and 410 are also connected to bitlines 314 and 316, wordlines 418and 420 may be configured to be at substantially the same potential asbitlines 314 and 316 to hinder current from flowing from wordline 418and/or wordline 420 to bitline 314 and/or bitline 316.

Furthermore, it may be desirable to hinder currents from flowing fromwordline 308 into memory cells 404 and 414. To do so, bitlines 426 and430 may be configured to be at substantially the same potential aswordline 308 to hinder current from flowing from wordline 308 to bitline426 via memory cell 404 and to hinder current from flowing from wordline308 to bitline 430 via memory cell 414. In addition, bitlines 424 and428 may be configured at a lower potential than wordline 308 so thatcurrent is hindered from flowing from bitline 424 to wordline 308through memory cell 404 and from bitline 428 to wordline 308 throughmemory cell 414.

Other memory cells not connected to either wordline 308 or bitlines 314and 316 (i.e., memory cells 402, 406, 412, and 416) may be configured tohinder consumption of current as is illustrated in FIG. 6. For example,bitlines 424 and 428 may be configured at the same potential aswordlines 418 and 420 to hinder current from flowing through left-handdiodes of memory cells 402, 406, 412, and 416. Furthermore, bitlines 426and 430 and wordlines 418 and 420 may be configured to reverse biasright-hand diodes of memory cells 402, 406, 412, and 416.

The above discussion has assumed that memory element 302 is configuredso that memory element 302 changes to a low-resistance state when avoltage greater than the turn-on voltage of memory element 302 isapplied between electrodes 306 and 304 so that electrode 306 is at ahigher potential than electrode 304. Similarly, the above discussion hasassumed that memory element 302 changes to a high-resistance state whena voltage greater than the turn-off voltage of memory element 302 isapplied across electrodes 304 and 306 so that electrode 304 is at ahigher potential than electrode 306.

However, memory element 302 may be reversed so that memory element 302changes to a high-resistance state when a voltage greater than theturn-off voltage of memory element 302 is applied between electrodes 306and 304 so that electrode 306 is at a higher potential than electrode304. In this configuration, memory element 302 may change to alow-resistance state when a voltage greater than the turn-on voltage ofmemory element 302 is applied across electrodes 304 and 306 so thatelectrode 304 is at a higher potential than electrode 306.

Furthermore, the above discussion has assumed that a high-resistancestate of memory element 302 corresponds to a bit value of “0” and that alow-resistance state of memory element 302 corresponds to a bit value of“1.” However, as was mentioned above, memory devices may be constructedbased on an understanding that the high-resistance state of memoryelement 302 corresponds to a bit value of “1” and that thelow-resistance state of memory element 302 corresponds to a bit value of“0” without changing the principles of writing and reading memory cell300.

The above discussion has referred to a memory element having a highresistance state and a low resistance state. However, in someembodiments of the invention, a memory element may be configurable inmore than two different resistive states. Such a memory element maystore more than one bit of information and may be used in a memory cellsuch as memory cell 300. Each of a plurality of different programmingvoltages may correspond to a different one of a plurality of differentresistive states of the memory element.

The methods of programming memory cell 300 described above may beadapted to program a memory element having more than one resistive stateby applying one of the plurality of programming voltages to the memoryelement in order to configure the memory element in the resistive statecorresponding to the applied programming voltage. Furthermore, themethods of reading memory cell 300 described above may be adapted toread the memory element by comparing a current resulting from a voltageapplied to the memory element to a plurality of different referencecurrents to determine in which of the plurality of different resistivestates the memory cell is configured.

In compliance with the statute, the subject matter disclosed herein hasbeen described in language more or less specific as to structural andmethodical features. It is to be understood, however, that the claimsare not limited to the specific features shown and described, since themeans herein disclosed comprise example embodiments. The claims are thusto be afforded full scope as literally worded, and to be appropriatelyinterpreted in accordance with the doctrine of equivalents.

1. A memory cell comprising: a wordline; a first bitline; a secondbitline; and a memory element electrically connected to the wordline andselectively electrically connected to the first bitline and to thesecond bitline, the memory element storing information via a resistivestate of the memory element; wherein the memory cell is configured toconvey the resistive state of the memory element via either a firstcurrent flowing from the first bitline through the memory element to thewordline or a second current flowing from the wordline through thememory element to the second bitline.
 2. The memory cell of claim 1wherein: the memory cell further comprises a first diode and a seconddiode; the memory element comprises a first electrode connected to thefirst bitline via the first diode and to the second bitline via thesecond diode and a second electrode connected to the wordline; and thememory element is electrically connected to the first bitline via thefirst diode when the first diode is forward biased and is electricallydisconnected from the first bitline when the first diode is not forwardbiased; and the memory element is electrically connected to the secondbitline via the second diode when the second diode is forward biased andis electrically disconnected from the second bitline when the seconddiode is not forward biased.
 3. The memory cell of claim 1 wherein thememory element comprises at least one of an ionic conductingchalcogenide, a binary metal oxide, a perovskite oxide, a colossalmagnetoresistive, or a polymer.
 4. The memory cell of claim 1 whereinthe memory element is configured to store the information in anon-volatile manner in the absence of a voltage or a current.
 5. Amemory cell programming method comprising: providing a memory cellcomprising a wordline, first and second bitlines, and a memory element,the memory element being electrically connected to the wordline andselectively electrically connected to the first and second bitlines;using the memory element, storing information via a first resistivestate of the memory element; applying a first voltage across thewordline and the first bitline effective to electrically disconnect thefirst bitline from the memory element; and applying a second voltageacross the wordline and the second bitline effective to electricallyconnect the second bitline to the memory element and to configure thememory element in a different second resistive state.
 6. The method ofclaim 5 further comprising: providing a first diode connected to a firstelectrode of the memory element and to the first bitline, the firstdiode being reverse biased due to the first voltage and the firstvoltage being less than a breakdown voltage of the first diode; andproviding a second diode connected to the first electrode of the memoryelement and to the second bitline; wherein: a second electrode of thememory element is connected to the wordline; the memory element ishighly conductive of current between the second electrode and the firstelectrode when the memory element is in the first resistive state; andthe memory element is highly resistive of current between the secondelectrode and the first electrode when the memory element is in thesecond resistive state.
 7. The method of claim 6 wherein the appliedsecond voltage is greater than a sum of a turn-off voltage of the memoryelement and a cut-in voltage of the second diode.
 8. The method of claim5 wherein the applied first voltage is substantially the same as theapplied second voltage.
 9. The method of claim 5 further comprisingsubsequent to the applying of the first voltage and the applying of thesecond voltage: applying a third voltage across the second bitline andthe wordline effective to electrically disconnect the second bitlinefrom the memory element; and applying a fourth voltage across the firstbitline and the wordline effective to electrically connect the firstbitline to the memory element and to configure the memory element in thefirst resistive state.
 10. The method of claim 9 wherein the appliedthird voltage is substantially the same as the applied fourth voltage.11. A memory cell reading method comprising: providing a memory cellcomprising a wordline, first and second bitlines, and a memory elementelectrically connected to the wordline and selectively electricallyconnected to the first and second bitlines, the memory element beingdisposed to be selectively configured in any of a plurality of differentresistive states; applying a first voltage across the wordline and thefirst bitline effective to electrically disconnect the first bitlinefrom the memory element; applying a second voltage across the wordlineand the second bitline effective to cause a current to flow from thewordline through the memory element to the second bitline; and based onthe current, determining that the memory element is configured in aparticular one of the plurality of different resistive states.
 12. Themethod of claim 11 wherein the particular one of the plurality ofdifferent resistive states is associated with a value of a bit ofinformation.
 13. The method of claim 11 wherein the memory element isdisposed to be selectively configured in either a high resistance stateor a low resistance state.
 14. The method of claim 11 furthercomprising: providing a first diode connected to a first electrode ofthe memory element and to the first bitline; and providing a seconddiode connected to the first electrode of the memory element and to thesecond bitline; wherein the applied second voltage is greater than acut-in voltage of the second diode but less than a sum of the cut-involtage of the second diode and a turn-off voltage of the memory elementand the memory element comprises a second electrode connected to thewordline.
 15. The method of claim 11 wherein the determining comprisescomparing the current to a reference current.
 16. The method of claim 11wherein the determining comprises determining that the current is verysmall or immeasurable and that the memory element is in a highresistance state. 17-25. (canceled)